| 摘要 |
PROBLEM TO BE SOLVED: To provide a method and a device for logic verification which can verify logical equivalence even when the number of input ports of a low-layer block and the logic of an input port are different. SOLUTION: After the logic of a low-layer block X' is verified, the low-layer block X' is excluded from objects of comparison and the logic of a circuit C' of a high layer is verified; even when input ports B of the low-layer block X' increase as the circuit is altered, the logical equivalence of the circuit C' of the high layer is verified by using equivalence information of the input ports B.
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