| 摘要 |
PROBLEM TO BE SOLVED: To decrease the number of registers to be used concerning a processor capable of using a target register from the issue of an instruction to the write of the result in the register. SOLUTION: When there are live ranges A and B, the live ranges A and B are overlapped, a position locating the terminating instruction of A follows a position locating the terminating instruction of B, the latency of the leading instruction of B is fixed at compiling and the position locating the terminating instruction of B is preceding to a position, following the position locating the leading instruction of A just by the latency cycle of the leading instruction of A, the same register as the target register of the leading instruction of A is used for the target register of the leading instruction of B, so that the number of registers to be used can be decreased.
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