| 摘要 |
One embodiment of the present invention provides a system for synthesizing a circuit that allocates propagation delay between modules in the circuit based upon wireload information. The system receives a circuit divided into modules coupled together by a number of signal lines. The system defines a first set of timing constraints, and uses the first set of timing constraints to compile the circuit from a hardware description language specification into a first gate-level implementation. Next, the system performs a timing analysis on the first gate-level implementation to determine positive or negative slack values for the signal lines. These slack values specify amounts of extra propagation delay available on the signal lines. Next, the slack values are used to define a second set of timing constraints by allocating the slack values between the modules based upon wireload information. This wireload information may include such parameters as gate delays and drive strengths for gates coupled to the signal lines. The second set of timing constraints is used to compile the circuit into a second gate-level implementation. If necessary, the process of compilation, timing analysis and allocation of slack values may be repeated until the circuit meets all timing constraints.
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