ARRAY ARCHITECTURE AND OPERATING METHODS FOR DIGITAL MULTILEVEL NONVOLATILE MEMORY INTEGRATED CIRCUIT SYSTEM
摘要
A high speed voltage mode sensing is provided for a digital multibit non-volatile memory integrated system. An embodiment has a local source follower stage followed by a high speed common source stage. Another embodiment has a local source follower stage followed by a high speed source follower stage. Another embodiment has a common source stage followed by a source follower. An auto zeroing scheme is used. A capacitor sensing scheme is used. Multilevel parallel operation is described.
申请公布号
EP1145248(A2)
申请公布日期
2001.10.17
申请号
EP20000908291
申请日期
2000.01.13
申请人
AGATE SEMICONDUCTOR, INC.
发明人
TRAN, HIEU, VAN;KHAN, SAKHAWAT, M.;KORSH, GEORGE, J.