| 摘要 |
In one embodiment, a spacer layer (22) is formed overlying a gate electrode (16), which is formed on a semiconductor substrate (12). The spacer layer (22) is then etched to form a sidewall spacer (24). A scanning electron microscope (SEM) is then used to measure the width of the sidewall spacer (24). The measured value for the width of the sidewall spacer (24) is then used to adjust a subsequent integrated circuit fabrication process, such as a spacer etch process, an implant process, or an anneal process. As a result, transistors with improved drain saturation currents are fabricated.
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