| 摘要 |
A method of generating and distributing clock signals is described. The method provides synchronous clock signals in as many phases as a designer of a given circuit finds useful. The method acknowledges timing constraints of the controlled system, and adjusts the clock phases appropriately to meet the needs of the local data circuits using the clock signals. The method uses stages of clock signal generators which are coupled to appropriate portions of the datapath and to each other for controlling the datapath and to provide information about clock signal timing to each other. By adding delay elements, the method can also be used to test the design of the given circuit.
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