发明名称 Method and apparatus for performing latency based hazard detection
摘要 Performing hazard detection in a processor that exhibits register latencies between execution units. The opcode classes of producer and consumer instructions are determined. Using these opcode classes, the register latency between the producer and consumer instructions is determined, and a register status signal is sent.
申请公布号 US6304955(B1) 申请公布日期 2001.10.16
申请号 US19980223241 申请日期 1998.12.30
申请人 INTEL CORPORATION 发明人 ARORA JUDGE K.
分类号 G06F9/38;(IPC1-7):G06F9/38 主分类号 G06F9/38
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