| 摘要 |
A clock generator supplying clock signals to a synchronous system is disabled in response to a first synchronous signal from the synchronous system and enabled in response to an asynchronous signal. Upon the enabling of the clock generator in response to the synchronous signal, a second synchronous signal is transmitted to the synchronous system to notify the system that the clock generator is enabled. In the preferred embodiment, the register bits in a shift register are set by the first synchronous signal to a value that disables the clock generator and then the register bits can be set by an asynchronous signal to a value that enables, or wakes up, the clock generator. The first synchronous signal that is used to disable the clock generator is also used to initiate a synchronous counter that counts a pre-established number of clock signals from the clock generator and then transmits a synchronous wake-up signal to the synchronous system. Utilizing the counter and the shift register allows a clock generator to be restarted with an asynchronous signal while maintaining clean separation between the synchronous and asynchronous domains of an electrical system.
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