| 摘要 |
PROBLEM TO BE SOLVED: To provide a high resolution digital phase control circuit of power- saving and small area type where increase in power consumption and in the circuit occupied area are minimized. SOLUTION: The digital phase control circuit 10 consists of a voltage controlled delay line VCDL1 where delay buffers G1-G10 whose propagation delay time is 160 ps are connected in cascade, a voltage controlled delay line VCDL2 where delay buffers H1-H8 whose propagation delay time is 200 ps are connected in cascade, a selection circuit S2 that extracts a clock signal from any stage of the voltage controlled delay line VCDL1 and outputs the signal to a first stage of the voltage controlled delay line VCDL2, and a selection circuit S3 that extracts and outputs a clock signal from any stage of the voltage controlled delay line VCDL2. Delay locked loops DLL1, DLL2 apply feedback control to the voltage controlled delay line VCDL1 and the second voltage controlled delay line VCDL2 to control the phase of a clock signal where the difference of 40 ps between the 160 ps and the 200 ps is used for the resolution. |
