CLOCK GENERATING CIRCUIT

摘要

PROBLEM TO BE SOLVED: To provide a clock generating circuit with which a clock with desired frequencies is obtained without requiring any high speed or highly precise PLL, or without generating the incase of current consumption or the increase of a chip area. SOLUTION: This clock generating circuit is provided with a frequency- dividing circuit 12 for generating a clock signal CK200 with 200 MHz by frequency-halving a clock signal CK400 from a PLL circuit 11, a delay circuit 13 for generating 5 phase clocks clk0-clk4 having phase delay by 1 ns each with 200 MHz by delaying the signal CK200 by 1 ns each, an edge detecting circuit 14 for generating 5 phase pulse signals out0-out4 having phase delay by 1 ns each in 5 ns cycles by detecting each rising edge of the 5 phase clocks, an OR circuit 15 for generating a pulse signal PL1 in a 1 GHz cycle (1 ns cycle) by calculating the logical sum of the 5 phase pulse signals, a frequency- dividing circuit 16 for generating a clock signal CK500 with 500 MHz by frequency-halving the pulse signal PL1, and a multi-phase clock generating circuit 17 for generating 250 MHz/4 phase outputs CL1-CL4 based on the signal CK500.