发明名称 LOGIC VERIFICATION METHOD AND DEVICE
摘要 PROBLEM TO BE SOLVED: To perform an operation simulation of a logic circuit including gate circuits and flip-flop circuits so as to easily clarify the cause of malfunction, regarding a logic verification method and a device thereof which verify the authenticity of the logic of the logic circuit. SOLUTION: Prior to executing operation simulation, a tag that distinguishes between a clock signal and a data signal is added to each input signal for objective logic circuit of the operation simulation. While the operation simulation is performed, in the case an output of a gate circuit in the logic circuit varies in response to the change of inputted clock signal, a tag of clock signal is added to the signal of the output, in the case the output varies in response to the change of inputted data signal, a tag of data signal is added to the signal of the output and these output signals are permitted to propagate, and in case a signal having a tag of data signal is inputted to a clock input terminal of the flip-flop circuit in the logic circuit, a message is outputted.
申请公布号 JP2001282883(A) 申请公布日期 2001.10.12
申请号 JP20000093706 申请日期 2000.03.30
申请人 KAWASAKI STEEL CORP 发明人 SUGAYA MASAYUKI
分类号 G06F17/50;(IPC1-7):G06F17/50 主分类号 G06F17/50
代理机构 代理人
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