| 摘要 |
A semiconductor device can reduce parasitic capacitance between the pad portion of the gate electrode and the body region of a DTMOS on an SOI substrate. In an element forming region of an SOI substrate (1), an electrode portion (6NA) of a gate electrode (6N) is formed on the upper surface of an SOI layer (4) with a gate oxide film (5N) in between. In an element isolation region of the SOI substrate (1), a pad portion (6NB) of the gate electrode (6N) is formed on an element isolation insulation film (9), and a contact hole (11N) is selectively formed in the upper surface of an interlayer insulation film (10), extending through the element isolation insulation film (9) to the upper surface of the SOI layer (4). A sidewall of the pad portion (6NB) of the gate electrode (6N) is in contact with a W plug (21) which fills the contact hole (11N).
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