发明名称 |
SINGLE RAIL DOMINO LOGIC FOR FOUR-PHASE CLOCKING SCHEME |
摘要 |
A single rail domino logic circuit (Figure 1) using a four-phase clocking scheme. A stacked PMOS pair (123, 125) provides a quarter clock cycle precharge time. The quarter clock cycle precharge time allows for placement of an additional inverter in the output signal (19) path to form both an output signal and a complement of the output signal (21) for use in subsequent logic stages.
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申请公布号 |
WO0076068(A3) |
申请公布日期 |
2001.10.11 |
申请号 |
WO2000US15533 |
申请日期 |
2000.06.05 |
申请人 |
S3 INCORPORATED |
发明人 |
ABDEL-HAFEEZ, SALEH;RANJAN, NALINI |
分类号 |
H03K19/096;(IPC1-7):H03K19/096 |
主分类号 |
H03K19/096 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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