发明名称 Circuit arrangement for reception of at least two digital signals
摘要 The circuit arrangement includes a calibration circuit (2) which is connected with connections (11, 12) for at least two digital signals (E1, E2), and which comprises outputs (13, 14) for at least two digital output signals (Al, A2) which are respectively derived from one of the digital signals. A temporal control of a switching flank of one of the output signals results through the calibration circuit using a control value (R). A comparison circuit (3) is connected with the outputs (13, 14), and comprises a connection for a comparison signal (V) which indicates, that one of the output signals has a switching flank preceding that of the other output signal. The calibration circuit includes a memory circuit (4) for storing the control value, and a control input (21), over which the control value is adjustable using the condition of the comparison signal of the comparison circuit.
申请公布号 DE10016724(A1) 申请公布日期 2001.10.11
申请号 DE20001016724 申请日期 2000.04.04
申请人 INFINEON TECHNOLOGIES AG 发明人 NIKUTTA, WOLFGANG
分类号 H03K5/00;H03K5/135;H03K5/26;H03L7/081;H04L7/00;(IPC1-7):H03K5/125;G01R31/318 主分类号 H03K5/00
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