| 摘要 |
This Rambus DRAM has a power save function which is not restricted in using time and has a short setting time, by forcibly compensating for a lost capacitor value in a memory cell to have a predetermined value, when a power save mode is changed to a normal mode. The Rambus DRAM includes: a memory core unit having a plurality of memory cells and a refresh counter; a packet controller for analyzing a packet control signal applied from an external channel, and generating a control signal for controlling a power mode; a power mode controller for generating each power mode signal and a self refresh enable signal for controlling the operation of the refresh counter according to the control signal; and a delay locked loop controlled according to the power mode signals, for adjusting a phase difference between a clock signal applied from the external channel and a clock signal used in a semiconductor memory device, generating to the power mode controller a signal notifying that the mode can be changed to a normal mode, and compensating for a current value lost in a capacitor of the memory cell.
|
