MULTI-TIERED MEMORY BANK HAVING DIFFERENT DATA BUFFER SIZES WITH A PROGRAMMABLE BANK SELECT
摘要
An apparatus having a core processor and a plurality of cache memory banks is disclosed. The cache memory banks are connected to the core processor in such a way as to provide substantially simultaneous data accesses for said core processor
申请公布号
WO0175607(A2)
申请公布日期
2001.10.11
申请号
WO2001US10573
申请日期
2001.03.30
申请人
INTEL CORPORATION;RAMAGOPAL, HEBBALALU, S.;ALLEN, MICHAEL;FRIDMAN, JOSE;HOFFMAN, MARC
发明人
RAMAGOPAL, HEBBALALU, S.;ALLEN, MICHAEL;FRIDMAN, JOSE;HOFFMAN, MARC