| 摘要 |
The present invention relates to a synchronization circuit and method for allowing two or more successive read processes of a memory to be activated simultaneously without destroying the paths or the data. Two independent read processes are mutually independent while active, and are synchronized with respect to each other. The connection between a plurality of sense amplifiers and an output buffer is also synchronized by protocol conditions. The synchronization circuit further synchronizes the read streams so that an evaluation step is perfomed exclusively on one of the plurality of banks of memory while having a plurality of simultaneous read streams.
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