| 摘要 |
A serial modem (14) having a phase-locked loop (22), a central processing unit (20), a serial buffer (26) and a universal asynchronous receiver transmitter (UART) (28), wherein the serial buffer (26) and the UART (28) are connected to a host device (10) via an asynchronous serial interface (32). The central processing unit (20) enters a sleep mode when data is not being received. A start bit is received at a predetermined baud rate via the asynchronous serial interface (32). An interrupt is activated to start a wake-up transition at the central processing unit (20) upon receipt of the start bit. A series of bits following the start bit is sampled and stored in the serial buffer (26) until the central processing unit (20) is enabled. After the central processing unit (20) is enabled, a remainder of the series of bits are sampled and stored at the UART (28).
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