| 摘要 |
There is disclosed, for use in an x86-compatible processor capable of operating in real mode and paging mode and having a physically-addressable cache, an address translation device for providing physical addresses to the cache. The address translation device comprises: 1) a tag array for storing received untranslated addresses in selected ones of N tag entries in the tag array during real mode operations and paging mode operations; and 2) a data array for storing translated physical addresses corresponding to the untranslated addresses in selected ones of N data entries in the data array, wherein the untranslated addresses stored in the tag array during real mode operations are physical addresses equal to the corresponding translated physical addresses stored in the data array.
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