发明名称 |
Method to form transistors with multiple threshold voltages (VT) using a combination of different work function gate materials |
摘要 |
A method of forming a gate electrode, comprising the following steps. A semiconductor substrate having an overlying patterned layer exposing a portion of the substrate within active area and patterned layer opening. The patterned layer having exposed sidewalls. Internal spacers are formed over a portion of the exposed substrate portion within the patterned layer opening on the patterned layer exposed sidewalls. The internal spacers being comprised of a WF1 material having a first work function. A planarized gate electrode body is formed within the remaining portion of the patterned layer opening and adjacent to the internal spacers. The gate electrode body being comprised of a WF2 material having a second work function. The internal spacers and the gate electrode body forming the gate electrode.
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申请公布号 |
US6300177(B1) |
申请公布日期 |
2001.10.09 |
申请号 |
US20010768488 |
申请日期 |
2001.01.25 |
申请人 |
CHARTERED SEMICONDUCTOR MANUFACTURING INC. |
发明人 |
SUNDARESAN RAVI;PAN YANG;LEE JAMES YONG MENG;LEUNG YING KEUNG;PRADEEP YELEHANKA RAMACHANDRAMURTHY;ZHENG JIA ZHEN;CHAN LAP;QUEK ELGIN |
分类号 |
H01L29/43;H01L21/28;H01L21/336;H01L21/8234;H01L21/8238;H01L27/092;H01L29/423;H01L29/49;H01L29/78;(IPC1-7):H01L21/336;H01L21/476 |
主分类号 |
H01L29/43 |
代理机构 |
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