发明名称 Process, voltage, and temperature insensitive two phase clock generation circuit
摘要 A two phase clock generation circuit uses a current mirror and a crossbar switch to generate true and complement output clock signals that are relatively insensitive to process, voltage, and temperature variations. The current mirror generates a charging current and a discharging current that have a fixed magnitude ratio. The crossbar switch then alternately couples the charging current and the discharging current to the true and complement outputs of the clock generation circuit to generate the output clock signals. A selection signal generation unit is provided for generating the selection signal(s) required to appropriately control the switch. Because the charging and discharging currents are at fixed magnitudes and the crossbar switch is a balanced structure, the output clock signals remain aligned to a high degree of accuracy over a wide variety of conditions.
申请公布号 US6300812(B1) 申请公布日期 2001.10.09
申请号 US20000672340 申请日期 2000.09.28
申请人 INTEL CORPORATION 发明人 RUHL GREGORY E.;NARENDRA SIVA G.;DE VIVEK K.
分类号 H03K5/151;(IPC1-7):G01R25/00 主分类号 H03K5/151
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