发明名称 Double-edge-triggered flip-flop providing two data transitions per clock cycle
摘要 An apparatus comprising a clock for providing a clock signal, means for providing a delayed version of the clock signal, two transparent latches having clock inputs controlled by opposite polarities of the delayed clock signal, a multiplexer having (i) inputs fed by outputs of the latches, and (ii) a select input fed by the clock signal, and means for providing a select signal for selecting the latch whose clock is inactive. Preferably, each of the latches has a scan input gate and a scan output gate, and the scan output of the first latch is applied to the scan input of the second latch to form a scannable latch pair. Also, preferably, the apparatus further comprises a data port for applying data to the first and second latches, and an exclusive OR gate at the data port, whereby the apparatus produces a gated clock signal. Also disclosed is a method of operating this apparatus.
申请公布号 US6300809(B1) 申请公布日期 2001.10.09
申请号 US20000616551 申请日期 2000.07.14
申请人 INTERNATIONAL BUSINESS MACHINES CORPORATION 发明人 GREGOR ROGER PAUL;HATHAWAY DAVID JAMES;LACKEY DAVID E.;OAKLAND STEVEN FREDERICK
分类号 H03K3/012;H03K3/037;(IPC1-7):H03K3/12;H03K3/286;H03K3/356 主分类号 H03K3/012
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