发明名称 MRAD test circuit, semiconductor memory device having the same and MRAD test method
摘要 A multi-row active disturb (MRAD) test circuit, a semiconductor memory device having the test circuit, and an MRAD test method are provided. The semiconductor memory device includes at least one memory array including a plurality of word lines sharing a bit line sense amplifier. Furthermore, in the semiconductor memory device, at least two word lines among the plurality of word lines, which have a bit line sense amplifier in common, are activated simultaneously in an MRAD test mode. The test circuit includes a control signal generating circuit and a row decoder. The control signal generating circuit is a circuit for generating a plurality of control signals and generates at least one activated control signal in an MRAD test mode. The row decoder activates at least two word lines by a control signal and a predetermined row address signal comprised of a plurality of bits. The test circuit and the test method provide a reduction in test time for a semiconductor memory device without increase in current consumption.
申请公布号 US6301170(B2) 申请公布日期 2001.10.09
申请号 US20010766733 申请日期 2001.01.22
申请人 SAMSUNG ELECTRONICS CO., LTD. 发明人 JANG TAE-SEONG
分类号 G11C29/34;G11C29/00;G11C29/32;(IPC1-7):G11C7/00 主分类号 G11C29/34
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