| 摘要 |
To reduce the power consumption and to shorten the transmission delay time in a signal line drive for the purpose of transmitting a binary signal. The NMOS transistors 10, 12 are respectively connected as driving switching elements between the transmission end of a complementary pair of bus lines (AL, AL_) and a terminal at the power supply voltage (VSS) of a reference L level. The switching control circuit 14 for the purpose of controlling the ONsquareOFF switching of the NMOS transistor 10 is constructed of the PMOS transistor 16, the NMOS transistor 18, the inverters 20, 22, the NAND gate 24, and the NOR gate 26. The switching control circuit 34 for the purpose of controlling the ONsquareOFF switching of the NMOS transistor 12 is constructed of the PMOS transistor 36, the NMOS transistor 38, the inverter 40, the NAND gate 42, and the NOR gate 44. The PMOS transistors 46, 48 used as bias or as switching elements for the precharge are respectively connected between the transmission ends of both bus lines (AL, AL_) and a terminal at the power supply voltage (VDD).
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