Synchronous type semiconductor memory device permitting reduction in ratio of area occupied by control circuit in chip area

摘要

An address signal is transmitted to each bank by a common address bus. A column pre-decoder, and a row pre-decoder detect a selection of a corresponding bank in response to a signal transmitted by the address bus, and receive an address signal in response to a command signal from a command data bus. Circuits closer to the side of the address data bus and command data bus than to the circuit which latches the received data have a hierarchical power supply configuration.