| 摘要 |
An intermediate stage for a rail-to-rail input/output CMOS opamp includes a floating current source separating two current mirrors (151-154,155-158), where the ideal current source includes a floating current mirror (500,501,502,503,504,505) enabling an output quiescent current to be provided which does not vary with changes in the voltage rails or the common-mode input voltage, and enabling elimination of input offset caused by the mismatch of the two current sources (164,166). The NMOS transistor (502) has a source-drain path provided in series with a PMOS transistor (505) serving to connect the current mirrors (151-154) and (155-158) and to eliminate input offset. The source of transistor (500) is separated from the VSS and VDD rails by a PMOS transistor 503 and current source (508) enabling the current mirror (500,501,502,503,504,505) to float so that transistors (502) and (505) will each have a gate to source bias voltage independent of changes in the voltage on the voltage supply rails VDD and VSS and independent of any input common-mode voltage offset. Voltage clamping transistors (600) and (602) can further be included to enable the current mirror transistors (151-154) and (155-158) to be low voltage devices to increase overall operation speed and device matching.
|
