发明名称 Programmable logic device input/output architecture with power bus segmentation for multiple I/O standards
摘要 In a programmable logic device, input/output circuits are grouped into blocks. Each block includes input/output circuits capable of handling a plurality of logic signalling schemes, which may require different supply voltages and reference voltages. Each block also has its own power supply bus. In this way, the different blocks can be provided with different supply and reference voltages, so that different blocks can be used for different logic signalling schemes, thereby allowing more than one such scheme to be used simultaneously on a single device. A single block could also be implemented with more than one scheme active, as long as all of the schemes in use in the block have the same power supply requirements and-to the extent that each such scheme requires a reference voltage-the same reference voltage requirements.
申请公布号 US6300790(B1) 申请公布日期 2001.10.09
申请号 US19990366938 申请日期 1999.08.04
申请人 ALTERA CORPORATION 发明人 VEENSTRA KERRY;RANGASAYEE KRISHNA;TURNER JOHN E.
分类号 H03K19/173;H03K19/177;(IPC1-7):H03K19/173 主分类号 H03K19/173
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