发明名称 |
Method for manufacturing semiconductor device |
摘要 |
A implantation step of a dopant ion for forming source and drain regions (S and D) is divided into one implantation of a dopant ion for forming a p/n junction with a well region (3), and one implantation of a dopant ion that does not influence a position of the p/n junction between the source and drain regions (S and D) and the well region with a shallow implantation depth and a large implantation amount. After conducting an activation heat treatment of the dopant, a surface of the source/drain region is made into cobalt silicide 12, so that the source/drain region (S and D) can have a low resistance, and a p/n junction leakage can be reduced.
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申请公布号 |
US6300206(B1) |
申请公布日期 |
2001.10.09 |
申请号 |
US20000486899 |
申请日期 |
2000.03.03 |
申请人 |
HITACHI, LTD.;HITACHI ULSI SYSTEMS CO., LTD. |
发明人 |
FUKADA SHINICHI;HASHIMOTO NAOTAKA;KOJIMA MASANORI;MOMIJI HIROSHI;ABE HIROMI;SUZUKI MASAYUKI |
分类号 |
H01L21/336;H01L21/8238;H01L29/10;(IPC1-7):H01L21/331 |
主分类号 |
H01L21/336 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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