| 摘要 |
PROBLEM TO BE SOLVED: To shorten largely a test time by improving an activation rate of a word line only at the time of a test of a row system without changing constitution of DRAM cores, in a DRAM-mixed logic LSI. SOLUTION: This LSI is provided with a memory cell array in which DRAM cells are arranged in a matrix state, plural word lines connected commonly to respective memory cell of the same row in a memory cell array, plural bit lines connected commonly to respective memory cell of the same row in a memory cell array, plural block selecting circuit 14 outputting a block selecting signal dividing the memory cell array into plural cell arrays 13 in accordance with contents of the prescribed plural bits out of an address signal and selecting, and a test circuit 10 controlling block selecting signals outputted from plural block selecting circuits so that all signals are made an activation state at the time of test of a circuit of a row system of the memory cell array. |
