发明名称 DELAY PROFILE MEASUREMENT METHOD AND DELAY PROFILE MEASUREMENT CIRCUIT
摘要 <p>PROBLEM TO BE SOLVED: To provide a delay profile measurement circuit that can measure delay profile (detection of a path of a delayed wave) in a CDMA receiver. SOLUTION: In-phase summing sections 30a, 30b, that adaptively change number of data summed in phase, depending on a frequency of fading divide a received data stream with a pilot symbol inserted thereto into a plurality of blocks, and provide an output of the results of in-phase summation, while gradually changing the number of summed blocks. An in-phase summing number decision circuit 40 calculates a power of a received signal corresponding to each summing result, compares them to obtain an optimum in-phase summing number (M). A power calculation section 50 calculates power on the basis of data of the decided summing number.</p>
申请公布号 JP2001274724(A) 申请公布日期 2001.10.05
申请号 JP20000084368 申请日期 2000.03.24
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 YAMADA DAISUKE
分类号 H04B1/707;H04B1/7113;H04B1/7115 主分类号 H04B1/707
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