发明名称 METHOD AND SYSTEM FOR OVERLAY EXPOSURE
摘要 PROBLEM TO BE SOLVED: To improve a throughput by performing alignment of a substratum pattern and an upper layer pattern with high accuracy and in a short time. SOLUTION: An exposure method for exposing the upper layer pattern overlaid on the substratum pattern comprises the following steps: A coordinate measuring device 11 for measuring the position of a mark on a wafer is provided so as to be adjacent to an aligner 12. In the coordinate measuring device 11, the marks in the chips on the wafer are respectively measured to determine positional deformation of the pattern in the surfaces of the chips, and the marks at four points on the different chips are measured to determine deformation due to chip alignment in a wafer surface. In the aligner 12, the marks at the four points on the different chips are measured to determine deformation due to chip alignment in a wafer surface, and the alignment of the substratum pattern and the upper layer pattern is performed based on the chip alignment deformation and the positional deformation in the surface of the chip which is obtained by the coordinate measuring device 11. A subsequent wafer is measured in the coordinate measuring device 11 during exposing the wafer in the aligner 12.
申请公布号 JP2001274073(A) 申请公布日期 2001.10.05
申请号 JP20000088412 申请日期 2000.03.28
申请人 TOSHIBA CORP 发明人 KATO YOSHIMITSU
分类号 G03F7/20;G03F9/00;H01L21/027;(IPC1-7):H01L21/027 主分类号 G03F7/20
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