发明名称 MULTIPROCESSOR SYSTEM
摘要 PROBLEM TO BE SOLVED: To rewrite an optional memory area in a sub controller having an address space larger than that of a main controller from the main controller side. SOLUTION: The main controller 10 outputs an address signal AD1 to an address signal line 31 and also outputs an area designation signal BK to a designation signal line 34. The expansion address generating part 24 of the sub controller 20 side converts the signal AD1 on the basis of the signal BK, generates an address signal AD2 having an address space larger than that of the signal AD1 and gives the signal AD2 to an address terminal A of an EEPROM 22. Thus, it is possible to write a data signal DT given through a data line 32 in an optional area of the EEPROM 22.
申请公布号 JP2001273146(A) 申请公布日期 2001.10.05
申请号 JP20000086597 申请日期 2000.03.27
申请人 OKI ELECTRIC IND CO LTD 发明人 SAKURAI TOSHIO
分类号 G06F15/177;G06F9/445;G06F12/02;(IPC1-7):G06F9/445 主分类号 G06F15/177
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