发明名称 FAILURE ANALYSIS TEST DEVICE AND REGISTER CIRCUIT
摘要 PROBLEM TO BE SOLVED: To always generate a normal signature even to an undefined value output from an unused function block and to easily perform a failure analysis of an integrated circuit, etc., in a short time while securing high reliability. SOLUTION: An observation register circuit first preserves mask data inputted through an AND circuit 2 instead of shift data in a register 7 through a register 4. The AND circuit 5 is disconnected to prevent the input of an undefined value by storing 0 as the mask data in the register 7 in the case of being connected to a non-scanning circuit having a possibility of outputting an undefined value because the conduction and disconnection of the circuit 5 are controlled by the preserved value of the register 7. Then, in this case, the shift data of the preceding stage is preserved only in the register 4 through an AND circuit 2 and an exclusive OR circuit 3 to exclude the influence of the undefined value.
申请公布号 JP2001273159(A) 申请公布日期 2001.10.05
申请号 JP20000087392 申请日期 2000.03.27
申请人 TOSHIBA CORP 发明人 MORI JUNJI;ONOZAKI YASUTOMO
分类号 G01R31/28;G06F11/22 主分类号 G01R31/28
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