发明名称 PHASE LOCK LOOP AND STATIC PHASE ERROR CONTROL METHOD
摘要 PROBLEM TO BE SOLVED: To provide a phase lock loop in restoration of a wideband channel clock and a static phase error control method for the same. SOLUTION: The phase lock loop which is inputted with an EFM signal and a PLL clock signal, detects a frequency and phase and forms the PLL clock signal synchronized with the EFM signal by regulating control current with the result thereof includes a charge pump 140, a first low-pass filter 150, a voltage control oscillator 170 and a static phase error control section 160. The charge pump 140 regulates the control current according to the result of the detection. The first low-pass filter 150 outputs a control voltage by low- pass filtering of the output of the charge pump. A voltage control oscillator 170 provides a differential output voltage between the control voltage and a reference voltage, converts the differential output voltage to differential output current, extends the oscillation output current by the converted differential output current and forms the PLL clock signal. The static phase error control section 160 compares the control voltage and a triangular wave signal having a prescribed period and magnitude and changes the reference voltage according to the result thereof.
申请公布号 JP2001273725(A) 申请公布日期 2001.10.05
申请号 JP20010028161 申请日期 2001.02.05
申请人 SAMSUNG ELECTRONICS CO LTD 发明人 SAI TOMEI
分类号 G11B20/14;H03L7/08;H03L7/087;H03L7/089;H03L7/099;H03L7/113 主分类号 G11B20/14
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