发明名称 TRY-STATE BUFFER CIRCUIT
摘要 PROBLEM TO BE SOLVED: To provide a tri-state buffer circuit that realizes high circuit integration of a semiconductor integrated circuit in spite of its small size. SOLUTION: The tri-state buffer circuit is provided with an AND means 12 that ANDs an input signal IN and a control signal OE and provides an output of the inverted AND result, a P-channel TR QP1 that has a gate receiving a signal outputted from the AND means, a source receiving a 1st power supply voltage, and provides an output of an output signl from a drain, a 1st N-channel TR QN1. that is in complementary connection with the P-channel TR, and a 2nd N-channel TR QN that supplies a current from the source of the 1st N-channel TR to a 2nd power supply according to a control signal.
申请公布号 JP2001274672(A) 申请公布日期 2001.10.05
申请号 JP20010007914 申请日期 2001.01.16
申请人 SEIKO EPSON CORP 发明人 ASAKURA TORU
分类号 H01L21/8234;H01L21/82;H01L27/02;H01L27/088;H03K19/0175;H03K19/094;(IPC1-7):H03K19/017;H01L21/823 主分类号 H01L21/8234
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