| 摘要 |
PROBLEM TO BE SOLVED: To provide a division unit capable of accelerating a processing speed by ignoring useless processing. SOLUTION: This division unit is constructed by cascading the number of arithmetic circuits corresponding to the numbers of bits of a divisor and a dividend while shifting them to the low-order bit side of the dividend as much as prescribed bits at a time, and calculates a quotient and a remainder obtained by sequentially performing processing from the arithmetic circuit on the top stage to divide the dividend by the divisor. Each of the arithmetic circuits detects the most significant bit of '1' in a bit string to be a comparison object with the divisor, controls the operations of the respective arithmetic circuits so as to jump processing by the respective arithmetic circuits to perform processing in accordance with the number of '0s' continuing from the most significant bit of the bit string, outputs the bit of the quotient of a corresponding digit in accordance with results obtained by comparing the divisor with the bit string and outputs the bit string or a bit string obtained by subtracting the divisor from the bit string as a partial remainder or a remainder. |
