发明名称 METHOD AND DEVICE FOR VERIFYING FINE-GRADED VALIDITY OF BEHAVIORAL MODEL OF CENTRAL PROCESSING UNIT
摘要 PROBLEM TO BE SOLVED: To more quickly detect an error on a design by making it possible to verify a CPU with grading finer than that of the conventional practice in a test of a computer system. SOLUTION: A macroinstruction is decomposed into microinstructions, and each microinstruction is sequentially carried out. The sequence of the microinstructions is decided by an emulated microinstruction sequencer (220) by using dynamic performance information including information obtained as a result of performing the preceding macroinstruction in the sequence of the microinstructions. When the performance of each microinstruction is finished, a reference state (115) is compared with the corresponding state of a behavioral model, and the difference between them is notified. After the whole microinstructions in the sequence of the microinstructions are carried out, a reference state is compared with a corresponding state of a behavioral model and the difference between them is notified.
申请公布号 JP2001273165(A) 申请公布日期 2001.10.05
申请号 JP20010031392 申请日期 2001.02.07
申请人 HEWLETT PACKARD CO <HP> 发明人 JEREMY PETSINGER;SAFFORD KEVIN DAVID;CARL P BURUMERU;BROCKMANN RUSSELL C;BRUCE A LONG;KNEBEL PATRICK
分类号 G06F11/28;G06F9/22;G06F11/26;G06F17/50;H02H3/05;(IPC1-7):G06F11/26 主分类号 G06F11/28
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