发明名称 SYSTEM AND METHOD FOR CHECKING DESIGN RULE AND DESIGN RULE CHECK PROGRAM RECORDING MEDIUM
摘要 PROBLEM TO BE SOLVED: To design an integrated circuit which surely satisfies a design rule and also to shorten the time required for verifying whether a relevant rule is satisfied. SOLUTION: In the system where a design s checked about an integrated circuit consisting of plural cells, a prescribed distance is set between each of input/output cells 2 arranged around a cell area 1 and other input/output cells. Since this set distance differs according to the wiring materials, a space is secured by a distance corresponding to the wiring material that requires the longest distance. In other words, the cell space is decided in response to the minimum wiring space corresponding to the wiring material that is decided by a design rule. It is verified whether the integrated circuit that is produced according to the decided cell space is accordant with the design rule. Thus, the time required for verification is shortened since verification can be omitted about combinations with other cells.
申请公布号 JP2001273349(A) 申请公布日期 2001.10.05
申请号 JP20000084883 申请日期 2000.03.24
申请人 SEIKO EPSON CORP 发明人 OKI YUJI
分类号 G06F17/50;H01L21/82;(IPC1-7):G06F17/50 主分类号 G06F17/50
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