| 摘要 |
A parallel processor and an image processing system incorporating such processor are disclosed. Control signals in the parallel processor are generated by an instruction sequence control unit, and divided into two: global control signals supplied to a local signal generator of arbitrary selected processor element group; and local control signals buffered by the local control signal generator and then supplied exclusively to the processor elements included in arbitrary selected processor element group. This construction of the processor alleviates deterioration in device characteristics and undesirable increase in driving power requirements.
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