| 摘要 |
<p>An architecture of a FLASH memory organized in a plurality of physical sectors wherein read, write and erase operations of data occupying a fractional memory space of any one of said physical sectors are carried out, may include splitting a physical sector in a plurality of singularly addressable logic sectors. Each logic sector (j) is defined by a memory space of pre-established size (PAYLOADj), a chain pointer (CHAIN_PTRj) assuming a neutral value (NULL) or a value pointing directly or indirectly to a second logic sector associated to a respective chain pointer (CHAIN_PTR2) at neutral value (NULL), a status indicator (STATUSj) assuming a first value (FREE) if the logic sector is empty, a second value (OD) if the data contained in it belongs to the logic sector, a third value (NOD) if the data do not belong to the logic sector, or a fourth value (DEL) if the data has been erased, and a remap pointer (REMAP_PTRj) assuming the neutral value (NULL) or a value pointing directly or indirectly to the chain pointer (CHAIN_PTR3) of a third logic sector. A further improvement consists in attributing to each physical sector a logical address (LOGICAL_ADDRESS) permitting to destine to the function of temporary buffer, for partly erasing the content of a physical sector, in rotation all the physical sectors, not to repeatedly stressing the same sector. <IMAGE></p> |
