Current comparison type latch

摘要

In a current comparison type latch, during a reset mode of the current comparison type latch where the clock signal is at the "L" level, transistors which are disposed along the current path extending from the high potential power supply line to the low potential power supply line are turned OFF while transistors which connect the high potential power supply line to two output terminals are turned ON, so as to bring the potential of each of the two output terminals to a logic level (the "H" level or the "L" level), thereby preventing a through current from flowing from the high potential power supply line to the low potential power supply line. Therefore, a high-speed and high-precision current comparison is made while reducing the through current during a reset mode.