发明名称 |
SEMICONDUCTOR MEMORY DEVICE ALLOWING INCREASE IN CAPACITY AND OPERATION SPEED WITH A SUPPRESSED LAYOUT AREA |
摘要 |
A column select gate of a semiconductor memory device includes read gate circuits. Each read gate circuit includes read gate transistors. Each read gate transistor connects a read column select line to a global I/O line pair in response to a potential level on a bit line pair received on its gate and the potential on the read column select line. A voltage drop caused on one of the paired global I/O lines by turn-on of the read gate transistor is amplified by a main read amplifier to obtain read data.
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申请公布号 |
US2001026496(A1) |
申请公布日期 |
2001.10.04 |
申请号 |
US19990451709 |
申请日期 |
1999.12.01 |
申请人 |
HIDAKA HIDETO |
发明人 |
HIDAKA HIDETO |
分类号 |
G11C11/409;G11C7/10;G11C11/401;G11C11/4096;G11C29/04;(IPC1-7):G11C8/12 |
主分类号 |
G11C11/409 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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