TECHNIQUES FOR IMPROVING MEMORY ACCESS IN A VIRTUAL MEMORY SYSTEM

摘要

According to the present invention, methods and apparatus for reducing memory access latency are disclosed. When a new entry is made to translation look aside buffer (110), the new TLB entry points to a corresponding TLB page of memory (108). Concurrently with the updating of the TLB (110), the TLB page is moved temporally closer to a processor (102) by storing the TLB page in a TLB page cache (114). The TLB page cache (114) is temporally closer to the processor (102) than is a main memory (108).