| 摘要 |
There are provided a vertical MOS transistor in which a high frequency characteristic is improved by reducing a feedback capacitance, and a method of manufacturing the same. When a gate voltage is applied to a gate electrode, a channel is formed in a p- epitaxial growth layer along a trench, and an electron current flows from an n+ drain layer to the p- epitaxial growth layer. In this case, an overlapping area between a gate and the drain layer through a gate oxide film is smaller than prior art, and the capacitance between the gate and the drain layer is smaller than the prior art. Thus, the feedback capacitance becomes small and the high frequency characteristic is improved. Further, since a portion of the gate oxide film at the bottom of the trench is thicker than the portion at the side wall, the distance between the gate and the n+ semiconductor substrate becomes larger than the prior art, and the capacitance formed between the gate and the n+ semiconductor substrate is smaller than the prior art. Thus, the high frequency characteristic is improved as compared with the prior art.
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