发明名称 Dual clock domain read fifo
摘要 A first-in first-out buffer (FIFO) with multiple outputs. The FIFO has an input for writing data into the FIFO. The FIFO has multiple outputs for reading the data out of the FIFO. Each output is independent from the other outputs, and can be used to read data from a different address at a different time using a different clock signal. In one embodiment, the FIFO is implemented as a storage array with circular pointers to repeatedly loop through the addressable locations. It includes a write pointer to indicate which address represents the input. It includes multiple read pointers to indicate which addresses represent the outputs. Overrun prevention logic is used to assure that the write pointer will not cause new data to be written into any address that has not been read by all outputs, and to assure that data will not be read from any address that has not been written into.
申请公布号 AU3095901(A) 申请公布日期 2001.10.03
申请号 AU20010030959 申请日期 2001.01.16
申请人 INTEL CORPORATION 发明人 ANDREW M. VOLK;MICHAEL W. WILLIAMS
分类号 G06F5/10 主分类号 G06F5/10
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