| 摘要 |
An EPROM writing circuit including: a cell array consisting of an EPROM cell; a word line decoder and a bit line decoder for respectively decoding an address and a writing signal and enabling corresponding word lines and bit lines among a plurality of word lines and bit lines; a level sensing unit for sensing a level of an inputted booster voltage and outputting a level sensing signal; a decoding unit for ANDing the level sensing signal and the writing signal and outputting it; a first, a second and a third power switches enabled by the decoding signal, for supplying the sensed voltage to a voltage distribution unit; a voltage distribution unit enabled by the output voltage of the power switches, for stepping down the booster voltage to a different voltage level and outputting it; and a switching unit for outputting the stepped-down voltage to the cell array, by which degradation of the EPROM gate due to the excessive writing which is caused when the applied voltage Vpp is high is prevented and the problem in that the writing time becomes excessively lengthened when the applied voltage Vpp is low is automatically prevented.
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