| 摘要 |
An apparatus is described for controlling refresh of a multibank DRAM. A memory controller includes refresh request circuitry having a refresh counter and address incrementer. The refresh counter produces a refresh request signal, with the address incrementer producing an associated refresh address. The refresh request and address are handled much like a memory read operation, with the associated read data being ignored. In one implementation, the refresh request is given priority over any other pending memory access request. Refresh operations are initiated without first waiting for all DRAM banks to be precharged, thereby avoiding the significant time penalties associated with the prior art.
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