Phase lock loop system and method

摘要

Symmetrical cross coupled PLL circuits provide pseudo-synchronization between two independent clock signals, especially for use in fault tolerant applications. Independent oscillators provide input signals to each of the PLL circuits. The PLL circuits include divide circuitry that provide output signals at some sub multiple of the input clock signals. The phase relationship between the output clock signals from the cross coupled PLL circuits is monitored by phase detector circuits. If the phase of one output clock signal is determined to be advanced relative to the other output clock signal, the phase of that output clock signal is retarded by temporarily increasing the divide ratio of the PLL circuit producing the phase advanced signal.