发明名称 High speed multiplier
摘要 The high speed multiplier takes advantage of results from previous calculations by recognizing that in many cases the multiplicand between a first and second multiplication differs only slightly. Thus, the present system divides the multiplicand into a cache lookup bit (CLB) and a table lookup bit (TLB). The results of a first multiplication are stored in a cache. The CLB of a of the multiplicand in the second multiplication is then compared to the CLB of the multiplicand in the second multiplication. If the CLB matches, the product of the first multiplication is retrieved. The product of the TLB of the multiplicand and the multiplier is then retrieved from a lookup table and either added or subtracted from the retrieved product.
申请公布号 US6298369(B1) 申请公布日期 2001.10.02
申请号 US19980164027 申请日期 1998.09.30
申请人 STMICROELECTRONICS, INC. 发明人 NGUYEN THI N.
分类号 G06F7/52;G06F7/523;G06F7/544;(IPC1-7):G06F7/52 主分类号 G06F7/52
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