发明名称 Semiconductor memory device and method for setting stress voltage
摘要 The present invention provides a semiconductor memory device that performs a burn-in test. The device includes word lines, pairs of bit lines, memory cells, sense amplifiers connected to the pairs of bit lines for amplifying a potential difference between the associated pair of bit lines, and a burn-in test control circuit for providing a stress voltage to the plurality of word lines and the pairs of bit lines to perform a burn-in test based on the burn-in control signal The burn-in test control circuit includes a potential difference setting circuit for selecting one of the first word lines so to generate a potential difference between at least one of the pairs of bit lines. The sense amplifiers amplify the potential difference to provide the stress voltage between the word lines and the associated pair of bit lines and between the bit lines of that pair.
申请公布号 US6297999(B2) 申请公布日期 2001.10.02
申请号 US20010784181 申请日期 2001.02.16
申请人 FUJITSU LIMITED 发明人 KATO YOSHIHARU;KAWAMOTO SATORU
分类号 G01R31/28;G11C11/401;G11C29/00;G11C29/06;G11C29/50;(IPC1-7):G11C29/00 主分类号 G01R31/28
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